Hackaday

CPLD Tutorial: Learn Programmable Logic The Easy Way

The guys over at hackshed have been busy. [Carl] is making programmable logic design easy with an 8 part CPLD tutorial. (March 2018: Link dead. Try the Wayback Machine.) Programmable logic devices are ...
Purdue University

Legacy Course Catalog

Description: Introduction to standard cell design of VLSI (Very Large Scale Integration) digital circuits using the VHDL hardware description language (Very High Speed Integrated Circuits Hardware ...
Hackaday

Reinventing VHDL Badly

A few years ago, Philip Peter started a little pet project. He wanted to build his own processor. This really isn’t out of the ordinary – every few months you’ll find someone with a new project to ...
EDN

New Protel Release to Include VHDL Design Entry

SYDNEY, AUSTRALIA-Altium Ltd. plans to include a new design capture product with the working name “nVisage” in the new version of its Protel board-level design system, Protel 99SE. nVisage is a fully ...
Electronics Weekly

ChipWorks can rebuild chip parts into schematics

US reverse engineering experts ChipWorks have developed a browser that rebuilds parts of any chip into schematics and VHDL or Verilog from an analysis of the different layers of the device. ChipWorks ...
Design-Reuse

Lattice Announces Improved Synthesis and Power Optimization in CPLD Design Tools

HILLSBORO, OR, Aug 16, 2010 -- Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced the immediate availability of Version 1.4 of its ispLEVER(R) Classic design tool suite. The ispLEVER ...
EDN

Putting the R in RTL : Coding Registers in Verilog and VHDL

Many years ago, when I was a young man and the Boston Red Sox had just lost the 1986 world series, controversy stalked the land of hardward development. A new technology called Register Transfer ...
Electronic Design

What’s the Difference Between VHDL, Verilog, and SystemVerilog?

Designers of electronic hardware describe the behavior and structure of system and circuit designs using hardware description languages (HDLs)—specialized programming languages commonly known as VHDL, ...
Design-Reuse

So-ADE Unveils Debugger for Use with Verific Design Automation's SystemVerilog, VHDL, UPF Parser Platforms

Saint Geoire En Valdaine, France -- May 21, 2015-- So-ADE today announced immediate availability of an easy-to-use and intuitive debugger for the development and debugging of the SystemVerilog, VHDL ...
Electronic Design

Facing Up To Today’s FPGA Verification Challenges

Fifteen years ago verification of FPGA designs was easy but as the size of FPGAs has increased so have the verification challenges, Jerry Kaczynski explains. Today it is not unusual for FPGA users to ...